The present invention relates to information processing networks, and more particularly to fault-tolerant means for transmitting data between a local station and one or more remote data handling stations of an information processing network.
For numerous data processing applications, it is advantageous to utilize a network with more than one processing location, and further with one or more of the processing stations physically remote from a central or "local" processing station. Linkages for serial transmission of data are readily available for linking remote I/O busses to the local processing station. However, because such links usually involve conversion of data to a form more suitable to long distance transmission, an increased number of components is required for the linkage, dramatically increasing the probability of a failure among the components comprising the linkage. This is true particularly when the linkage includes a fiberoptic line and the accompanying necessary transmitter-receiver devices for converting bit-encoded data into optical signals, as well as the reverse conversion.
A known technique in this situation is to provide one or more redundant paths, available for transmitting data in the event of a failure along the original path. Among the known approaches are dual-ring arrangements, for example as disclosed in U.S. Pat. No. 4,837,856 (Glista, Jr.). Glista discloses a fault-tolerant fiberoptic coupler/receiver in a terminal in a high-speed digital, audio or video data transmission system. Each terminal has one or more bypass lines, and is connected to at least one bypass line from an upstream terminal. Logic on the terminal selects an input from either the primary line or one of the received bypass lines, based on predetermined values. A pair of rings is disclosed, both of which carry data unidirectionally and in the same direction.
U.S. Pat. No. 4,835,763 (Lau) shows a dual-ring network in which the unidirectional rings transmit data in opposite directions. Each of a plurality of nodes in the network selects one of the rings from which to receive data, based upon error signals. Each node can insert error signals to all downstream traffic, based on an error detected upstream. U.S. Pat. No. 4,696,001 (Gagliardi et al) and U.S. Pat. No. 4,527,270 (Sweeton) also disclose dual-ring arrangements in which signals travel in opposite directions.
Another apparatus for fault-tolerant serial transmission is disclosed in U.S. Pat. No. 4,649,384 (Sheafor et al). Sheafor et al describes a system including communication circuits connected to a host CPU (central processing unit), local controllers, and a plurality of memory discs, in which multiple four-wire circuits transmit data in bit-serial format. Some of the circuits are dedicated to data block transmission at a first transfer rate, and others are used only for message transmission at a second transfer rate.
The devices described in the foregoing patents, while satisfactory in certain respects, fail to adequately address certain requirements of the network employed in connection with the present invention. In addition to the need for redundancy, a need for numerous I/O busses meant that attachment of the busses with point-to-point serial links would have created electrical loading and circuit card real estate problems at the processor interface due to the large number of I/O bus interface chips and accompanying optical components. Further, due to the need for further module and card I/O pins, more cards would have been required to contain the processor interface logic, with the addition of further cards being unacceptable in view of certain structural features of the system.
Therefore, it is an object of the present invention to provide a network in which a minimum number of components is required to attach remote I/O busses to processor interface logic at a local station, while at the same time providing at least one redundant path for data transmission.
Another object is to provide an information processing network in which remote busses are connected to a local processing configuration in a manner to reduce electrical loading at the processor interface.